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新一代的數位介面標準 (系列、記憶、顯示等) 迫使今日的相容性和偵錯工具本身限制面對多種高速 Tx 和 Rx 設計的問題,包括 -

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Library

Title
PCI Express® 發射器 PLL 測試 - 方法比較
有數種以所使用測試儀器類型為基礎量測 PLL 迴路回應的方法。如預期,多種方法會犧牲掉測試準確度、測試速度 (傳輸量)、易使用性、易設定性,和初始成本 。此外,某些方法的限制使它們無法適用在所有類型的 PLL。所有的方法可以針對特定規格進行相容性測試,部分還提供額外有用的資訊供時脈設計工程師進行最佳化的設計。
以 16G 光纖通道速率分析 SFP + 收發器的特性
研究針對 16G 光纖通道標準測試  SFP+ 收發器所需要的量測,涵蓋多模式 850 nm 和單一模式 Mode 1310 nm 介面。包含一個使用最新測試設備以 14.025 Gb/s 的 16G 線速率,單一模式 1310 nm 雷射 SFP+ 收發器進行。
PCIe Gen 5 Tx Tech Brief
Get an overview of PCI Express 5.0, testing, the challenges associated with that, and learn about the Tektronix PCIe 5.0 Transmitter Test Solution.
High Speed Interface Standards
This e-Guide will help you learn more about design challenges for testing PCIe 4.0, SAS, SuperSpeed USB, and DDR4 standards. Within the pages of the eGuide you will also get quick access to technical …
快速有效的 DVI 相容性量測挑戰解決方案
Tektronix 提供了所有您需要的 DVI 量測解決方案,從探測用的高頻寬數位螢光示波器 (DPO),到特定應用軟體。Tektronix 解決了如抖動和眼狀圖測試等棘手的量測問題,打要可自動化和簡化您工作的 DVI 解決方案。
Remote Head Acquisition Improves High Speed Serial Measurement
As high speed serial data rates continue to increase, the need to maximize margin in measurements increases. Coaxial cables, even good quality ones can impact the measurement margin. Remote heads for …
Probing Tips for High Performance Design and Measurement
When a high performance system or component needs to be verified, it often requires attaching an oscilloscope probe. For high speed circuits, the effect of attaching a probe often cannot be ignored …
Title
DDR5 Memory Characterization
While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges.  Learn about characterization and …
PCIe Gen5 to Gen6 and Comparison to Electrical Ethernet
Watch as David Bouse explains the evolution of PCI Express from Gen5 to Gen6. Then hear from Pavel Zivny as he and David discuss PAM4 signaling in PCIe and how it compares with PAM4 as applied in …
USB4 Webinar
View our USB4 Compliance and Characterization Test webinar to learn how you can address the measurement challenges associated with the new USB4 standard.
PCI Express Gen 5 Reference Clock Webinar
This webinar presents an overview of reference clock jitter requirements as they have evolved and offers techniques for making these low femtosecond measurements using a real time oscilloscope. 
DDR5 Test Challenges Webinar
Learn how you can address five of the thorniest measurement challenges associated with the new DDR5 standard. Get an update on the DDR5 Rx/Tx compliance test and insight in the latest characterization …
PCI Express Gen 5 Update Webinar
Cloud-based computing power, storage capacity, and network bandwidth have led to the development of the PCI Express 5.0 specification for 32.0 GT/s. This webinar starts with an overview of 5.0 …
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation
This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
Demystify MIPI D-PHY and C-PHY Transmitter and Receiver Physical Layer Test
During this webinar, you'll gain an understanding of MIPI test challenges for both MIPI high-speed physical layers. You'll also get useful tips and technical insights into characterizing and …