By David Akerson
Editor’s note: This is the first part in a 3-part series focused on PCI Express and the next generation PCIe 5.0 specification. In this installment, we look at the origins of this game-changing standard and its impact on the PC industry. In parts 2 and 3 of this series, we’ll dive deeper into PCIe Gen 5.0. Part 2 will discuss the differences between PCIe 4.0 and PCIe 5.0 while part 3 will delve into PCIe 5.0 testing considerations.
Do you remember being impressed when computer storage reached gigabytes of capacity and processer speeds topped out in the megahertz? If you’re like me, you’ll recall that in 1999, we reveled in the benefits of 30 gigabyte spinning hard drives, 500MHz CPUs and the ability to download songs off Napster over a 56-kilobyte modem. Today, multiple terabyte storage drives are commonplace (1,000x increase over 1999), and core processors speeds exceed 4GHz.
With the technology improvements, massive data storage and fast processors are enabling new and exciting capabilities. Artificial intelligence, virtual reality, and self-driving cars were only in science fiction movies—now in 2018 we are experiencing them first-hand. With many of these applications, data and the ability to process that data with extremely low latency has been critical to making them possible.
Let’s dig deeper into some of the technological advancements, in particular storage, multi-core CPUs and PCI Express, that are bringing science fiction fantasies to life.
One of the critical contributors to this world of new capability is the technology advancements made in data communications. Taking you back to 1999, connecting to the internet to access data occurred over copper telephone lines connected to a 56 KB modem. At 56,000 bits per second, it would take approximately 10 minutes to download an average 4 MB song.
Today, fiber optic communications with multi-mode fiber optic networks running at speeds up to 10 Gb/s and single-mode fiber optic networks are able to reach speeds up to 100 Gb/s. That song now downloads in fractions of a second. These data communication advancements, let us take large amounts of data generated from sensors in many devices, quickly process it in data centers and transfer it back to end points for real-time decision making. In turn, this is enabling a transition from human triggered communications to AI triggered communications, facilitating today’s smart cities, homes and cars.
Meanwhile, advancements in storage technology and CPUs are playing a big role in delivering the vast amounts of data required by futuristic applications.
In the storage space, NAND-based solid-state storage is quickly displacing hard disk drives (HDDs) by providing faster, lower latency data access. Today’s typical HDD has read speeds of approximately 250 MB/s with a latency of 4.1 ms. In other words, it’s really slow. By comparison, a typical PCIe SSD with the latest NAND is capable of 2,500 MB/s with 10 µs of latency.
On the CPU side, in 1999, Intel released it Pentium III processor with a 733 MHz clock frequency on 1 core. In 2017, Intel released the Core i7 8700K featuring a clock speed of 3.7 GHz with 6 cores supporting 12 threads. The result of these technology advancements is storage that can store and serve up a lot of data and CPUs that can crunch a lot of data with increasing speed.
So where does PCIe come into play in this equation? The short answer is PCIe is a critical technology linking data, processing and communications to make many of the science fiction concepts possible. PCIe is so critical because it can perform two functions within a computing architecture. PCIe can be used as a physical network interface for high throughput, low latency communication between computers in a local area network and it can be used to connect the CPU to computer peripherals, such as NAND based PCIe-based storage drives.
Originally arriving in 2003, the PCIe 1.0 specification offered a 2.5 GT/s transfer rate. Each successive generation has increased throughput rates with the PCIe 4.0 specification, ratified in 2017, delivering 16 GT/s. To keep pace with data center communication needs and enable new applications, the PCIe 5.0 specification is in development, which will increase throughput to 32 GT/s, while also meeting more demanding requirements for low latency and power efficiency. For applications, such as AI, machine learning, virtual reality, self-driving cars and others, the advancements in the processor, storage and the PCIe interconnect have been and will continue to be critical to remove performance-impacting bottlenecks.
Watching science fiction technologies become reality is certainly exciting. Where we once could only dream, futuristic technologies are becoming a part of our everyday lives. But let’s remember that it didn’t just happen by chance. It took engineering vision, expertise and yes lots of testing to make these technologies possible.
Past, present, and future technology advancements like those discussed here involve testing PCIe devices using test instruments that have protocol-aware capability to assist with debug problems related to putting devices into loopback, performing link training, and understanding root cause of persistent bit error rate (BER) problems. Every high-speed test lab requires flexible and capable test equipment to characterize and validate silicon, systems, and devices. At Tektronix, we’re committed to delivering solutions to meet your needs and enable world-changing innovation.
Tektronix has solutions supporting the test requirements of PCIe 1.0 through to highly advanced solutions to help those engineers fortunate enough to be working on the forthcoming PCIe 5.0 specification. For more information, visit https://www.tek.com/wired-communications/accelerate-pcie-sas-sata-test-and-debug
For Part 2 of this series, visit: